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2Gb: x16, x32 Mobile LPDDR2 SDRAM S4
PRECHARGE Command
Table 42: Bank Selection for PRECHARGE by Address Bits
BA2
BA1
BA0
Precharged Bank(s) Precharged Bank(s)
AB (CA4r)
0
0
0
0
0
0
0
0
(CA9r)
0
0
0
0
1
1
1
1
(CA8r)
0
0
1
1
0
0
1
1
(CA7r)
0
1
0
1
0
1
0
1
4-Bank Device
Bank 0 only
Bank 1 only
Bank 2 only
Bank 3 only
Bank 0 only
Bank 1 only
Bank 2 only
Bank 3 only
8-Bank Device
Bank 0 only
Bank 1 only
Bank 2 only
Bank 3 only
Bank 4 only
Bank 5 only
Bank 6 only
Bank 7 only
1
Don’t Care Don’t Care Don’t Care
All banks
All banks
READ Burst Followed by PRECHARGE
For the earliest possible precharge, the PRECHARGE command can be issued BL/2
clock cycles after a READ command. A new bank ACTIVATE command can be issued to
the same bank after the row precharge time ( t RP) has elapsed. A PRECHARGE com-
mand cannot be issued until after t RAS is satisfied.
The minimum READ-to-PRECHARGE time ( t RTP) must also satisfy a minimum analog
time from the rising clock edge that initiates the last 4-bit prefetch of a READ com-
mand. t RTP begins BL/2 - 2 clock cycles after the READ command.
If the burst is truncated by a BST command, the effective BL value is used to calculate
when t RTP begins.
Figure 48: READ Burst Followed by PRECHARGE – RL = 3, BL = 8, RU( t RTP(MIN)/ t CK) = 2
T0
T1
T2
T3
T4
T5
T6
T7
T8
CK#
CK
RL = 3
BL/2
col addr a Col addr a
CA[9:0]
Bank m
Bank m
Bank m
row addr
Row addr
t RTP
t RP
CMD
READ
NOP
NOP
NOP
PRECHARGE
NOP
NOP
ACTIVATE
NOP
DQS#
DQS
DQ
D OUT A0
D OUT A1
D OUT A2
D OUT A3
D OUT A4
D OUT A5
D OUT A6
D OUT A7
Transitioning data
PDF: 09005aef83f3f2eb
2gb_mobile_lpddr2_s4_g69a.pdf – Rev. N 3/12 EN
69
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2010 Micron Technology, Inc. All rights reserved.
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